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<title>Serial Peripheral Interface</title>

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</style><table class="infobox infobox-table"><caption class="infobox-title">Serial Peripheral Interface (SPI)</caption><tbody><tr><th scope="row" class="infobox-label">Type</th><td colspan="3" class="infobox-data">

<a href="Serial_communication" title="Serial communication">Serial communication</a> <a href="Bus_(computing)" title="Bus (computing)">bus</a></td></tr><tr><th colspan="4" class="infobox-header" style="background:#ccccff">Production history</th></tr><tr><th scope="row" class="infobox-label">Designer</th><td colspan="3" class="infobox-data">

<a href="Motorola" title="Motorola">Motorola</a></td></tr><tr><th scope="row" class="infobox-label">Designed</th><td colspan="3" class="infobox-data">

Around early 1980s<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Manufacturer</th><td colspan="3" class="infobox-data">

Various</td></tr><tr><th scope="row" class="infobox-label"><a href="Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">Daisy chain</a></th><td colspan="3" class="infobox-data">

<a href="#Daisy_chain_configuration">Depends</a> on devices</td></tr><tr><th scope="row" class="infobox-label">Connector</th><td colspan="3" class="infobox-data">

Unspecified</td></tr><tr><th colspan="4" class="infobox-header" style="background:#ccccff">Electrical</th></tr><tr><th scope="row" class="infobox-label">Max. voltage</th><td colspan="3" class="infobox-data">

Unspecified</td></tr><tr><th scope="row" class="infobox-label">Max. current</th><td colspan="3" class="infobox-data">

Unspecified</td></tr><tr><th colspan="4" class="infobox-header" style="background:#ccccff">Data</th></tr><tr><th scope="row" class="infobox-label">Width</th><td colspan="3" class="infobox-data">

1 bit (bidirectional)</td></tr><tr><th scope="row" class="infobox-label">Max. devices</th><td colspan="3" class="infobox-data">

<a href="#Multidrop_configuration">Multidrop</a> limited by slave selects. <a href="#Daisy_chain_configuration">Daisy chaining</a> unlimited.</td></tr><tr><th scope="row" class="infobox-label">Protocol</th><td colspan="3" class="infobox-data">

<a href="Full-duplex" class="mw-redirect" title="Full-duplex">Full-duplex</a> <a href="Serial_communication" title="Serial communication">serial</a></td></tr><tr><th colspan="4" class="infobox-header" style="background:#ccccff">Pinout</th></tr><tr><th scope="row" class="infobox-label">MOSI</th><td class="infobox-data infobox-data-a">

Master Out Slave In</td></tr><tr><th scope="row" class="infobox-label">MISO</th><td class="infobox-data infobox-data-a">

Master In Slave Out</td></tr><tr><th scope="row" class="infobox-label">SCLK</th><td class="infobox-data infobox-data-a">

Serial Clock</td></tr><tr><th scope="row" class="infobox-label"><span style="text-decoration:overline;">SS</span></th><td class="infobox-data infobox-data-a">

<a href="Slave_Select" class="mw-redirect" title="Slave Select">Slave Select</a> (one or more)</td></tr><tr><td colspan="4" class="infobox-below">

(pins may have <a href="#Alternative_terminology">alternative names</a>)</td></tr></tbody></table>

<p><b>Serial Peripheral Interface</b> (<b>SPI</b>) is a <a href="De_facto_standard" title="De facto standard">de facto standard</a> (with many <a href="#Variations">variants</a>) for <a href="Comparison_of_synchronous_and_asynchronous_signalling" title="Comparison of synchronous and asynchronous signalling">synchronous</a> <a href="Serial_communication" title="Serial communication">serial communication</a>, used primarily in <a href="Embedded_systems" class="mw-redirect" title="Embedded systems">embedded systems</a> for short-distance <a href="Wired_communication" title="Wired communication">wired communication</a> between <a href="Integrated_circuits" class="mw-redirect" title="Integrated circuits">integrated circuits</a>.

</p><p>SPI follows a <a href="Master%E2%80%93slave_(technology)" title="Master–slave (technology)">master–slave architecture</a>,<sup id="cite_ref-:0_2-0" class="reference"><a href="#cite_note-:0-2"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> where a master device <a href="Signaling_(telecommunications)" title="Signaling (telecommunications)">orchestrates communication</a> with one or more slave devices by driving the <a href="Clock_signal" title="Clock signal">clock</a> and <a href="Chip_select" title="Chip select">chip select</a> signals. Some devices support changing master and slave roles on the fly.

</p><p><a href="Motorola" title="Motorola">Motorola</a>'s original specification (from the early 1980s) uses four <a href="Logic_signal" class="mw-redirect" title="Logic signal">logic signals</a>, aka lines or wires, to support <a href="Full_duplex" class="mw-redirect" title="Full duplex">full duplex</a> communication. It is sometimes called a <i>four-wire</i> <a href="Serial_bus" class="mw-redirect" title="Serial bus">serial bus</a> to contrast with <a class="mw-selflink-fragment" href="#Three-wire">three-wire</a> variants which are <a href="Half_duplex" class="mw-redirect" title="Half duplex">half duplex</a>, and with the <i>two-wire</i> <a href="I%C2%B2C" title="I²C">I²C</a> and <a href="1-Wire" title="1-Wire">1-Wire</a> serial buses.

</p><p>Typical <a href="#Applications">applications</a> include interfacing <a href="Microcontrollers" class="mw-redirect" title="Microcontrollers">microcontrollers</a> with peripheral chips for <a href="Secure_Digital" class="mw-redirect" title="Secure Digital">Secure Digital</a> cards, <a href="Liquid_crystal_display" class="mw-redirect" title="Liquid crystal display">liquid crystal displays</a>, <a href="Analog-to-digital" class="mw-redirect" title="Analog-to-digital">analog-to-digital</a> and <a href="Digital-to-analog_converters" class="mw-redirect" title="Digital-to-analog converters">digital-to-analog converters</a>, <a href="Flash_memory#Serial_flash" title="Flash memory">flash</a> and <a href="EEPROM#Serial_bus_devices" title="EEPROM">EEPROM</a> memory, and various communication chips.

</p><p>Although SPI is a synchronous serial interface,<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> it is different from <a href="Synchronous_Serial_Interface" title="Synchronous Serial Interface">Synchronous Serial Interface</a> (SSI). SSI employs <a href="Differential_signaling" class="mw-redirect" title="Differential signaling">differential signaling</a> and provides only a single <a href="Simplex_communication" class="mw-redirect" title="Simplex communication">simplex communication</a> channel.

</p>

<div class="mw-heading mw-heading2"><h2 id="Operation">Operation</h2></div>

<p>Commonly, SPI has four logic signals. <a href="#Variations">Variations</a> may use different <a href="#Alternative_terminology">names</a> or have different signals.

</p>

<th>Description

</th></tr>

<tr>

<td><div class="center">Slave Select</div></td>

<td><a href="Logic_level#Active_state" title="Logic level">Active-low</a> <a href="Chip_select" title="Chip select">chip select</a> signal from master to<br>enable communication with a specific slave device

</td></tr>

<tr>

<td><div class="center">Serial Clock</div></td>

<td><a href="Clock_signal" title="Clock signal">Clock signal</a> from master

</td></tr>

<tr>

<td><div class="center">Master Out Slave In</div></td>

<td><a href="Serial_communication" title="Serial communication">Serial data</a> output from master

</td></tr>

<tr>

<td><div class="center">Master In Slave Out</div></td>

<td><a href="Serial_communication" title="Serial communication">Serial data</a> output from slave

</td></tr></tbody></table></dd></dl>

<p>MOSI on a master outputs to MOSI on a slave. MISO on a slave outputs to MISO on a master.

</p><p>Each device internally uses a <a href="Shift_register" title="Shift register">shift register</a> for serial communication, which together forms an inter-chip <a href="Circular_buffer" title="Circular buffer">circular buffer</a>.

</p><p>Slave devices should use <a href="Tri-state_output" class="mw-redirect" title="Tri-state output">tri-state outputs</a> so their MISO signal becomes <a href="High_impedance" title="High impedance">high impedance</a> (electrically disconnected) when the device is not selected. Slaves without tri-state outputs cannot share a MISO line with other slaves without using an external tri-state buffer.

</p>

<div class="mw-heading mw-heading3"><h3 id="Data_transmission">Data transmission</h3></div>

<p>To begin communication, the SPI master first selects a slave device by pulling its <span style="text-decoration:overline;">SS</span> low. (The bar above <span style="text-decoration:overline;">SS</span> indicates it is an <a href="Active_low" class="mw-redirect" title="Active low">active low</a> signal, so a low voltage means "selected", while a high voltage means "not selected")

</p><p>If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup>

</p><p>During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

</p><p>Transmission using a single slave involves one shift register in the master and one shift register in the slave, both of some given word size (e.g. 8 bits). The transmissions often consist of eight-bit words, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters.

</p><p>Data is usually shifted out with the <a href="Most-significant_bit" class="mw-redirect" title="Most-significant bit">most-significant bit</a> (MSB) first but the original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first. On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.

</p><p>If a single slave device is used, its <span style="text-decoration:overline;">SS</span> pin <i>may</i> be fixed to <a href="Logic_level" title="Logic level">logic low</a> if the slave permits it. With multiple slave devices, a <a href="#Multidrop_configuration">multidrop configuration</a> requires an independent <span style="text-decoration:overline;">SS</span> signal from the master for each slave device, while a <a href="#Daisy_chain_configuration">daisy-chain configuration</a> only requires one <span style="text-decoration:overline;">SS</span> signal.

</p><p>Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent <a href="Bus_contention" title="Bus contention">contention</a> on MISO, non-selected slaves must use <a href="Three-state_logic" title="Three-state logic">tristate</a> output. Slaves that are not already tristate will need external tristate buffers to ensure this.<sup id="cite_ref-Better_SPI_Bus_Design_in_3_Steps_5-0" class="reference"><a href="#cite_note-Better_SPI_Bus_Design_in_3_Steps-5"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="Clock_polarity_and_phase">Clock polarity and phase</h3></div>

<p>In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:4_7-0" class="reference"><a href="#cite_note-:4-7"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> named these two options as CPOL and CPHA (for <b>c</b>lock <b>pol</b>arity and <b>c</b>lock <b>pha</b>se) respectively, a convention most vendors have also adopted.

</p>

<p>The SPI <a href="Digital_timing_diagram" title="Digital timing diagram">timing diagram</a> shown is further described below:

</p>

<ul><li>CPOL represents the polarity of the clock. Polarities can be converted with a simple <a href="Inverter_(logic_gate)" title="Inverter (logic gate)">inverter</a>.

<ul><li>SCLK<sub>CPOL=0</sub> is a clock which idles at the <a href="Logical_low" class="mw-redirect" title="Logical low">logical low</a> voltage.</li>

<li>SCLK<sub>CPOL=1</sub> is a clock which idles at the logical high voltage.</li></ul></li>

<li>CPHA represents the <a href="Phase_(waves)" title="Phase (waves)">phase</a> of each data bit's transmission cycle relative to SCLK.

<ul><li>For CPHA=0:

<ul><li>The first data bit is output <i>immediately</i> when <span style="text-decoration:overline;">SS</span> activates.</li>

<li>Subsequent bits are output when SCLK transitions <i>to</i> its idle voltage level.</li>

<li>Sampling occurs when SCLK transitions <i>from</i> its idle voltage level.</li></ul></li>

<li>For CPHA=1:

<ul><li>The first data bit is output on SCLK's first clock edge <i>after</i> <span style="text-decoration:overline;">SS</span> activates.</li>

<li>Subsequent bits are output when SCLK transitions <i>from</i> its idle voltage level.</li>

<li>Sampling occurs when SCLK transitions <i>to</i> its idle voltage level.</li></ul></li>

<li>Conversion between these two phases is non-trivial.</li>

<li>MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.</li></ul></li></ul>

<div class="mw-heading mw-heading3"><h3 id="Mode_numbers">Mode numbers</h3></div>

<p>The combinations of polarity and phases are referred to by these "SPI mode" numbers with CPOL as the high order bit and CPHA as the low order bit:

</p>

<th>SPI mode

</th>

<th>Clock polarity<br>(CPOL)

</th>

<th>Clock phase<br>(CPHA)

</th>

<th>Data is shifted out on

</th>

<th>Data is sampled on

</th></tr>

<tr>

<td>0

</td>

<td>falling SCLK, and when <span style="text-decoration:overline;">SS</span> activates</td>

<td>rising SCLK

</td></tr>

<tr>

<td>1

</td>

<td>rising SCLK</td>

<td>falling SCLK

</td></tr>

<tr>

<td>0

</td>

<td>rising SCLK, and when <span style="text-decoration:overline;">SS</span> activates</td>

<td>falling SCLK

</td></tr>

<tr>

<td>1

</td>

<td>falling SCLK</td>

<td>rising SCLK

</td></tr></tbody></table>

<p>Notes:

</p>

<ul><li>Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1.</li>

<li>In Full Duplex operation, the master device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.</li>

<li>Different vendors may use different naming schemes, like CKE for clock edge or NCPHA for the inversion of CPHA.</li></ul>

<div class="mw-heading mw-heading3"><h3 id="Valid_communications">Valid communications</h3></div>

<p>Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's <a href="Scan_chain" title="Scan chain">scan chain</a> by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

</p>

<div class="mw-heading mw-heading3"><h3 id="Interrupts">Interrupts</h3></div>

<p>Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may be implemented optionally.

</p>

<div class="mw-heading mw-heading4"><h4 id="From_master_to_slave">From master to slave</h4></div>

<p>Microcontrollers configured as slave devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive <a href="FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a> buffer,<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> and may also set up an interrupt routine when their slave select input line is pulled low or high.

</p>

<div class="mw-heading mw-heading4"><h4 id="From_slave_to_master">From slave to master</h4></div>

<p>SPI slaves sometimes use an <a href="Out-of-band_signal" class="mw-redirect" title="Out-of-band signal">out-of-band signal</a> (another wire) to send an interrupt signal to a master. Examples include pen-down interrupts from <a href="Touchscreen" title="Touchscreen">touchscreen</a> sensors, thermal limit alerts from <a href="List_of_temperature_sensors" title="List of temperature sensors">temperature sensors</a>, alarms issued by <a href="Real-time_clock" title="Real-time clock">real-time clock</a> chips, <a href="Secure_Digital" class="mw-redirect" title="Secure Digital">SDIO</a><sup id="cite_ref-3wireSDI_9-0" class="reference"><a href="#cite_note-3wireSDI-9"><span class="cite-bracket">[</span>note 3<span class="cite-bracket">]</span></a></sup> and <a href="Audio_jack" class="mw-redirect" title="Audio jack">audio jack</a> insertions for an <a href="Audio_codec" title="Audio codec">audio codec</a>. Interrupts to master may also be faked by using <a href="Polling_(computer_science)" title="Polling (computer science)">polling</a> (similarly to <a href="USB_1.1" class="mw-redirect" title="USB 1.1">USB 1.1</a> and <a href="USB_2.0" class="mw-redirect" title="USB 2.0">2.0</a>).

</p>

<div class="mw-heading mw-heading3"><h3 id="Software_design">Software design</h3></div>

<p>SPI lends itself to a "bus driver" software design. Software for attached devices is written to call a "bus driver" that handles the actual low-level SPI hardware. This permits the driver code for attached devices to port easily to other hardware or a <a href="Bit-banging" class="mw-redirect" title="Bit-banging">bit-banging</a> software implementation.

</p>

<div class="mw-heading mw-heading3"><h3 id="Bit-banging_the_protocol">Bit-banging the protocol</h3></div>

<p>The <a href="Pseudocode" title="Pseudocode">pseudocode</a> below outlines a software implementation ("<a href="Bit-banging" class="mw-redirect" title="Bit-banging">bit-banging</a>") of SPI's protocol as a master with simultaneous output and input. This pseudocode is for CPHA=0 and CPOL=0, thus SCLK is pulled low before <span style="text-decoration:overline;">SS</span> is activated and bits are inputted on SCLK's rising edge while bits are outputted on SCLK's falling edge.

</p>

<ul><li>Initialize SCLK as low and <span style="text-decoration:overline;">SS</span> as high</li>

<li>Pull <span style="text-decoration:overline;">SS</span> low to select the slave</li>

<li>Loop for however many number of bytes to transfer:<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>note 4<span class="cite-bracket">]</span></a></sup>

<ul><li>Initialize<code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr"><span class="n">byte_out</span></code>with the next output byte to transmit</li>

<li>Loop 8 times:

<ul><li><a href="Left-shift_operator" class="mw-redirect" title="Left-shift operator">Left-Shift</a><sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>note 5<span class="cite-bracket">]</span></a></sup> the next output bit from<code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr"><span class="n">byte_out</span></code>to MOSI</li>

<li><a href="NOP_(code)" title="NOP (code)">NOP</a> for the slave's <a href="Setup_time" class="mw-redirect" title="Setup time">setup time</a></li>

<li>Left-Shift the next input bit from MISO into<code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr"><span class="n">byte_in</span></code></li>

<li>NOP for the slave's hold time</li>

<li><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr"><span class="n">byte_in</span></code>now contains that recently-received byte and can be used as desired</li></ul></li>

<li>Pull <span style="text-decoration:overline;">SS</span> high to unselect the slave</li></ul>

<p>Bit-banging a slave's protocol is similar but different from above. An implementation might involve <a href="Busy_waiting" title="Busy waiting">busy waiting</a> for <span style="text-decoration:overline;">SS</span> to fall or triggering an <a href="Interrupt_handler" title="Interrupt handler">interrupt routine</a> when <span style="text-decoration:overline;">SS</span> falls, and then shifting in and out bits when the received SCLK changes appropriately for however long the transfer size is.

</p>

<div class="mw-heading mw-heading2"><h2 id="Bus_topologies">Bus topologies</h2></div>

<p>Though the previous operation section focused on a basic interface with a single slave, SPI can instead communicate with multiple slaves using multidrop, daisy chain, or expander configurations.

</p>

<div class="mw-heading mw-heading3"><h3 id="Multidrop_configuration">Multidrop configuration</h3></div>

<p>In the <a href="Multidrop_bus" title="Multidrop bus">multidrop bus</a> configuration, each slave has its own <span style="text-decoration:overline;">SS</span>, and the master selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.

</p><p>

Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the slave is not selected. Slave devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its <span style="text-decoration:overline;">SS</span> signal.<sup id="cite_ref-Better_SPI_Bus_Design_in_3_Steps_5-1" class="reference"><a href="#cite_note-Better_SPI_Bus_Design_in_3_Steps-5"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> (Since only a single signal line needs to be tristated per slave, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four slave devices to an SPI bus)</p><blockquote><p>Caveat: All <span style="text-decoration:overline;">SS</span> signals should start high (to indicate no slaves are selected) before sending initialization messages to any slave, so other uninitialized slaves ignore messages not addressed to them. This is a concern if the master uses <a href="General-purpose_input/output" title="General-purpose input/output">general-purpose input/output (GPIO) pins</a> (which may default to an undefined state) for <span style="text-decoration:overline;">SS</span> and if the master uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for <span style="text-decoration:overline;">SS</span> to output a high voltage for <i>all</i> slaves <i>before</i> running initialization code from any of those software libraries. Another solution is to add a <a href="Pull-up_resistor" title="Pull-up resistor">pull-up resistor</a> on each <span style="text-decoration:overline;">SS</span>, to ensure that all <span style="text-decoration:overline;">SS</span> signals are initially high.<sup id="cite_ref-Better_SPI_Bus_Design_in_3_Steps_5-2" class="reference"><a href="#cite_note-Better_SPI_Bus_Design_in_3_Steps-5"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></p></blockquote>

<div class="mw-heading mw-heading3"><h3 id="Daisy_chain_configuration">Daisy chain configuration</h3></div>

<p>Some products that implement SPI may be connected in a <a href="Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">daisy chain</a> configuration, where the first slave's output is connected to the second slave's input, and so on with subsequent slaves, until the final slave, whose output is connected back to the master's input. This effectively merges the individual communication shift registers of each slave to form a single larger combined <a href="Shift_register" title="Shift register">shift register</a> that shifts data through the chain. This configuration only requires a single <span style="text-decoration:overline;">SS</span> line from the master, rather than a separate <span style="text-decoration:overline;">SS</span> line for each slave.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>

</p><p>In addition to using SPI-specific slaves, daisy-chained SPI can include <a href="Discrete_component" class="mw-redirect" title="Discrete component">discrete</a> shift registers for <a href="Shift_register#More_I/O_pins" title="Shift register">more pins</a> of inputs (e.g. using the <a href="Shift_register#Parallel-in_serial-out_(PISO)" title="Shift register">parallel-in serial-out</a> <a href="List_of_7400-series_integrated_circuits" title="List of 7400-series integrated circuits">74</a>xx165)<sup id="cite_ref-:3_13-0" class="reference"><a href="#cite_note-:3-13"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> or outputs (e.g. using the <a href="Shift_register#Serial-in_parallel-out_(SIPO)" title="Shift register">serial-in parallel-out</a> <a href="List_of_7400-series_integrated_circuits" title="List of 7400-series integrated circuits">74</a>xx595)<sup id="cite_ref-:2_14-0" class="reference"><a href="#cite_note-:2-14"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include <a href="SGPIO" title="SGPIO">SGPIO</a>, <a href="JTAG" title="JTAG">JTAG</a>,<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> and <a href="I2C" class="mw-redirect" title="I2C">I<sup>2</sup>C</a>.

</p>

<div class="mw-heading mw-heading3"><h3 id="Expander_configurations">Expander configurations</h3></div>

<p>Expander configurations use SPI-controlled addressing units (e.g. <a href="Binary_decoder" title="Binary decoder">binary decoders</a>, <a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">demultiplexers</a>, or shift registers) to add chip selects.

</p><p>For example, one <span style="text-decoration:overline;">SS</span> can be used for transmitting to a SPI-controlled demultiplexer an index number controlling its select signals, while another <span style="text-decoration:overline;">SS</span> is routed through that demultiplexer according to that index to select the desired slave.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="Advantages">Advantages</h3></div>

<ul><li>Full duplex communication in the default version of this protocol</li>

<li><a href="Push-pull_output" class="mw-redirect" title="Push-pull output">Push-pull drivers</a> (as opposed to <a href="Open_drain" class="mw-redirect" title="Open drain">open drain</a>) provide relatively good signal integrity and high speed</li>

<li>Higher <a href="Throughput" class="mw-redirect" title="Throughput">throughput</a> than <a href="I%C2%B2C" title="I²C">I²C</a> or <a href="System_Management_Bus" title="System Management Bus">SMBus</a>

<ul><li>SPI's protocol has no maximum clock speed, however:

<ul><li>Individual devices specify acceptable clock frequencies</li>

<li>Wiring and electronics limit frequency</li></ul></li></ul></li>

<li>Complete protocol flexibility for the bits transferred

<ul><li>Not limited to 8-bit symbols</li>

<li>Arbitrary choice of message size, content, and purpose</li></ul></li>

<li>Simple hardware and interfacing

<ul><li>Hardware implementation for slaves only requires a selectable shift register

<ul><li>Slaves use the master's clock and hence do not need precision oscillators</li>

<li>Slaves do not need a unique <a href="Address_space" title="Address space">address</a> – unlike <a href="I%C2%B2C" title="I²C">I²C</a> or <a href="GPIB" title="GPIB">GPIB</a> or <a href="SCSI" title="SCSI">SCSI</a></li>

<li>Masters only additionally require generation of clock and <span style="text-decoration:overline;">SS</span> signals</li>

<li>Results in simple bit-banged software implementation</li></ul></li>

<li>Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than <a href="Parallel_communication" title="Parallel communication">parallel interfaces</a>

<ul><li>At most one unique signal per device (<span style="text-decoration:overline;">SS</span>); all others are shared

<ul><li>The daisy-chain configuration does not need more than one shared <span style="text-decoration:overline;">SS</span></li></ul></li></ul></li>

<li>Typically lower power requirements than <a href="I%C2%B2C" title="I²C">I²C</a> or SMBus due to less circuitry (including pull up resistors)</li>

<li>Single master means no <a href="Bus_arbitration" class="mw-redirect" title="Bus arbitration">bus arbitration</a> (and associated failure modes) - unlike <a href="CAN-bus" class="mw-redirect" title="CAN-bus">CAN-bus</a></li>

<li>Transceivers are not needed - unlike <a href="CAN-bus" class="mw-redirect" title="CAN-bus">CAN-bus</a></li>

<li>Signals are unidirectional, allowing for easy <a href="Galvanic_isolation" title="Galvanic isolation">galvanic isolation</a></li></ul></li></ul>

<div class="mw-heading mw-heading3"><h3 id="Disadvantages">Disadvantages</h3></div>

<ul><li>Requires more pins on IC packages than <a href="I%C2%B2C" title="I²C">I²C</a>, even in <a class="mw-selflink-fragment" href="#Three-wire">three-wire</a> variants</li>

<li>Only handles short distances compared to <a href="RS-232" title="RS-232">RS-232</a>, <a href="RS-485" title="RS-485">RS-485</a>, or <a href="CAN-bus" class="mw-redirect" title="CAN-bus">CAN-bus</a> (though distance can be extended with the use of transceivers like <a href="RS-422" title="RS-422">RS-422</a>)</li>

<li>Extensibility severely reduced when multiple slaves using different SPI Modes are required

<ul><li>Access is slowed down when master frequently needs to reinitialize in different modes</li></ul></li>

<li>No formal standard

<ul><li>So validating conformance is not possible</li>

<li>Many existing variations complicate support</li></ul></li>

<li>No built-in protocol support for some conveniences:

<ul><li>No hardware <a href="Flow_control_(data)" title="Flow control (data)">flow control</a> by the slave (but the master can delay the next clock edge to slow the transfer rate)</li>

<li>No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it)</li>

<li>No error-checking protocol</li>

<li>No <a href="Hot_swapping" title="Hot swapping">hot swapping</a> (dynamically adding nodes)</li>

<li>Interrupts are outside the scope of SPI (see <a href="#Interrupts">§ Interrupts</a>)</li></ul></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Applications">Applications</h2></div>

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</style><div class="thumb tmulti tright"><div class="thumbinner multiimageinner" style="width:393px;max-width:393px"><div class="trow"><div class="tsingle" style="width:129px;max-width:129px"><div class="thumbimage" style="height:126px;overflow:hidden"><span typeof="mw:File"></span></div><div class="thumbcaption">SPI Memory by <a href="Atmel" title="Atmel">Atmel</a></div></div><div class="tsingle" style="width:129px;max-width:129px"><div class="thumbimage" style="height:126px;overflow:hidden"><span typeof="mw:File"></span></div><div class="thumbcaption"><a href="Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild</a> EEPROM using <a href="#Microwire">Microwire</a></div></div><div class="tsingle" style="width:129px;max-width:129px"><div class="thumbimage" style="height:126px;overflow:hidden"><span typeof="mw:File"></span></div><div class="thumbcaption"><a href="Microchip_Technology" title="Microchip Technology">Microchip</a> 32-Mbit <a href="#QPI/SQI">SQI</a> Flash Memory</div></div></div></div></div>

<p>SPI is used to talk to a variety of peripherals, such as

</p>

<ul><li>Sensors: <a href="Temperature" title="Temperature">temperature</a>, <a href="Pressure" title="Pressure">pressure</a>, <a href="Analog-to-digital_converter" title="Analog-to-digital converter">ADC</a>, <a href="Touchscreens" class="mw-redirect" title="Touchscreens">touchscreens</a>, <a href="Video_game_controllers" class="mw-redirect" title="Video game controllers">video game controllers</a></li>

<li>Control devices: <a href="Audio_codec" title="Audio codec">audio codecs</a>, digital potentiometers, <a href="Digital-to-analog_converter" title="Digital-to-analog converter">DACs</a></li>

<li>Camera lenses: <a href="Canon_EF_lens_mount" title="Canon EF lens mount">Canon EF lens mount</a></li>

<li>Memory: <a href="Flash_memory#Serial_flash" title="Flash memory">flash</a> and <a href="EEPROM#Serial_bus_devices" title="EEPROM">EEPROMs</a></li>

<li><a href="Real-time_clock" title="Real-time clock">Real-time clocks</a></li>

<li><a href="LCD" class="mw-redirect" title="LCD">LCDs</a>, sometimes even for managing image data</li>

<li>Any <a href="MultiMediaCard" title="MultiMediaCard">MMC</a> or <a href="Secure_Digital" class="mw-redirect" title="Secure Digital">SD</a> card (including <a href="Secure_Digital" class="mw-redirect" title="Secure Digital">SDIO</a> variant<sup id="cite_ref-3wireSDI_9-1" class="reference"><a href="#cite_note-3wireSDI-9"><span class="cite-bracket">[</span>note 3<span class="cite-bracket">]</span></a></sup>)</li>

<li><a href="Shift_registers" class="mw-redirect" title="Shift registers">Shift registers</a> for additional I/O<sup id="cite_ref-:3_13-1" class="reference"><a href="#cite_note-:3-13"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:2_14-1" class="reference"><a href="#cite_note-:2-14"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li></ul>

<p><a href="Printed_circuit_board" title="Printed circuit board">Board</a> real estate and wiring savings compared to a <a href="Parallel_communication" title="Parallel communication">parallel</a> bus are significant, and have earned SPI a solid role in embedded systems. That is true for most <a href="System-on-a-chip" class="mw-redirect" title="System-on-a-chip">system-on-a-chip</a> processors, both with higher-end 32-bit processors such as those using <a href="ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a>, <a href="MIPS_architecture" title="MIPS architecture">MIPS</a>, or <a href="PowerPC" title="PowerPC">PowerPC</a> and with lower-end microcontrollers such as the <a href="Atmel_AVR" class="mw-redirect" title="Atmel AVR">AVR</a>, <a href="PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">PIC</a>, and <a href="MSP430" class="mw-redirect" title="MSP430">MSP430</a>. These chips usually include SPI controllers capable of running in either master or slave mode. <a href="In-system_programming" title="In-system programming">In-system programmable</a> AVR controllers (including blank ones) can be programmed using SPI.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup>

</p><p>Chip or <a href="FPGA" class="mw-redirect" title="FPGA">FPGA</a> based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin. And for high-performance systems, <a href="FPGA" class="mw-redirect" title="FPGA">FPGAs</a> sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.

</p><p>The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as <a href="Digital_audio" title="Digital audio">digital audio</a>, <a href="Digital_signal_processing" title="Digital signal processing">digital signal processing</a>, or <a href="Channel_(communications)" class="mw-redirect" title="Channel (communications)">telecommunications channels</a>, but most off-the-shelf chips stick to half-duplex request/response protocols.

</p>

<div class="mw-heading mw-heading2"><h2 id="Variations">Variations</h2></div>

<p>SPI implementations have a wide variety of protocol variations. Some devices are transmit-only; others are receive-only. Slave selects are sometimes active-high rather than active-low. Some devices send the least-significant bit first. Signal levels depend entirely on the chips involved. And while the baseline SPI protocol has no command codes, every device may define its own protocol of command codes. Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols.

</p>

<div class="mw-heading mw-heading3"><h3 id="Original_definition">Original definition</h3></div>

<p><a href="Motorola" title="Motorola">Motorola</a> in 1983 listed<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> three <a href="Motorola_6805" class="mw-redirect" title="Motorola 6805">6805</a> 8-bit <a href="Microcomputer" title="Microcomputer">microcomputers</a> that have an integrated "Serial Peripheral Interface", whose functionality is described in a 1984 manual.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup>

</p>

<p>Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> (now under <a href="NXP_Semiconductors" title="NXP Semiconductors">NXP</a>, last revised 2002<sup id="cite_ref-:4_7-1" class="reference"><a href="#cite_note-:4-7"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>) informally serves as the "official" defining document for SPI.

</p>

<div class="mw-heading mw-heading3"><h3 id="Timing_variations">Timing variations</h3></div>

<p>Some devices have timing variations from Motorola's CPOL/CPHA modes. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response.

</p><p>Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the slave select line.

</p>

<div class="mw-heading mw-heading3"><h3 id="Transmission_size">Transmission size</h3></div>

<p>Different transmission word sizes are common. Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the <a href="JTAG" title="JTAG">JTAG</a> or <a href="SGPIO" title="SGPIO">SGPIO</a> protocols, or any other protocol that requires messages that are not multiples of 8 bits.

</p>

<div class="mw-heading mw-heading3"><h3 id="No_slave_select">No slave select</h3></div>

<p>Some devices do not use slave select, and instead manage protocol state machine entry/exit using other methods.

</p>

<div class="mw-heading mw-heading3"><h3 id="Connectors">Connectors</h3></div>

<p>Anyone needing an external connector for SPI defines their own or uses another standard connection such as: <a href="UEXT" title="UEXT">UEXT</a>, <a href="Pmod_Interface" title="Pmod Interface">Pmod</a>, various <a href="JTAG_connector" class="mw-redirect" title="JTAG connector">JTAG connectors</a>, <a href="Secure_Digital" class="mw-redirect" title="Secure Digital">Secure Digital</a> card socket, etc.

</p>

<div class="mw-heading mw-heading3"><h3 id="Flow_control">Flow control</h3></div>

<p>Some devices require an additional <a href="Flow_control_(data)" title="Flow control (data)">flow control</a> signal from slave to master, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a <i>ready</i> or <i>enable</i> signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.)

</p>

<div class="mw-heading mw-heading3"><h3 id="SafeSPI">SafeSPI</h3></div>

<p>SafeSPI<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

</p>

<div class="mw-heading mw-heading3"><h3 id="High_reliability_modifications">High reliability modifications</h3></div>

<p>In electrically noisy environments, since SPI has few signals, it can be economical to reduce the effects of <a href="Common_mode_signal" class="mw-redirect" title="Common mode signal">common mode noise</a> by adapting SPI to use <a href="Low-voltage_differential_signaling" title="Low-voltage differential signaling">low-voltage differential signaling</a>.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> Another advantage is that the controlled devices can be designed to loop-back to test signal integrity.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="Intelligent_SPI_controllers">Intelligent SPI controllers</h3></div>

<p>A <b>Queued Serial Peripheral Interface</b> (<b>QSPI</b>; different to but has same abbreviation as <i>Quad SPI</i> described in <a href="#Quad_SPI">§ Quad SPI</a>) is a type of SPI controller that uses a <a href="Queue_(data_structure)" class="mw-redirect" title="Queue (data structure)">data queue</a> to transfer data across an SPI bus.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> It has a <a href="Circular_buffer" title="Circular buffer">wrap-around</a> mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as <a href="Virtual_memory" title="Virtual memory">memory-mapped</a> parallel devices. This feature is useful in applications such as control of an <a href="Analog-to-digital_converter" title="Analog-to-digital converter">A/D converter</a>. Other programmable features in Queued SPI are chip selects and transfer length/delay.

</p><p>SPI controllers from different vendors support different feature sets; such <a href="Direct_memory_access" title="Direct memory access">direct memory access</a> (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by <b>Multichannel Buffered Serial Port</b> (<b>MCBSP</b>).<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>note 6<span class="cite-bracket">]</span></a></sup> Most SPI master controllers integrate support for up to four slave selects,<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>note 7<span class="cite-bracket">]</span></a></sup> although some require slave selects to be managed separately through GPIO lines.

</p><p>Note that <i>Queued SPI</i> is different from <i>Quad SPI</i>, and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode!<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="Microwire">Microwire</h3></div>

<p>Microwire,<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> often spelled <b>μWire</b>, is essentially a predecessor of SPI and a trademark of <a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a>. It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a <a class="mw-selflink-fragment" href="#Three-wire">three-wire</a> mode.

</p>

<div class="mw-heading mw-heading3"><h3 id="Microwire/Plus">Microwire/Plus</h3></div>

<p>Microwire/Plus<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.

</p>

<div class="mw-heading mw-heading3"><h3 id="Three-wire">Three-wire</h3></div>

<p>Three-wire variants of SPI restricted to a <a href="Half-duplex" class="mw-redirect" title="Half-duplex">half-duplex</a> mode use a single bidirectional data line called SISO (slave out/slave in) or MOMI (master out/master in) instead of SPI's two unidirectional lines (MOSI and MISO). Three-wire tends to be used for lower-performance parts, such as small EEPROMs used only during system startup, certain sensors, and <a class="mw-selflink-fragment" href="#Microwire">Microwire</a>. Few SPI controllers support this mode, although it can be easily <a href="Bit-banging" class="mw-redirect" title="Bit-banging">bit-banged</a> in software.

</p>

<p>For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted most-significant bit first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0.

</p><p>This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants:<sup id="cite_ref-W25Q16JV_30-0" class="reference"><a href="#cite_note-W25Q16JV-30"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-D25LQ64_31-0" class="reference"><a href="#cite_note-D25LQ64-31"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>

</p>

<ul><li>Dual read sends the command and address from the master in single mode, and returns the data in dual mode.</li>

<li>Dual I/O sends the command in single mode, then sends the address and return data in dual mode.</li></ul>

<p><b>Quad SPI</b> (<b>QSPI</b>; different to but has same abbreviation as <i>Queued-SPI</i> described in <a href="#Intelligent_SPI_controllers">§ Intelligent SPI controllers</a>) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.<sup id="cite_ref-W25Q16JV_30-1" class="reference"><a href="#cite_note-W25Q16JV-30"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-D25LQ64_31-1" class="reference"><a href="#cite_note-D25LQ64-31"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>

</p>

<dd>Commands sent on single line but addresses and data sent on four lines</dd>

<dd>Commands and addresses sent on a single line but data sent/received on four lines</dd></dl>

<p>Further extending quad SPI, some devices support a "quad everything" mode where <i>all</i> communication takes place over 4 data lines, including commands.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> This is variously called "QPI"<sup id="cite_ref-D25LQ64_31-2" class="reference"><a href="#cite_note-D25LQ64-31"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> (not to be confused with <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a>) or "serial quad I/O" (SQI)<sup id="cite_ref-SST26VF032B_33-0" class="reference"><a href="#cite_note-SST26VF032B-33"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup>

</p><p>This requires programming a configuration bit in the device and requires care after reset to establish communication.

</p>

<div class="mw-heading mw-heading3"><h3 id="Double_data_rate">Double data rate</h3></div>

<p>In addition to using multiple lines for I/O, some devices increase the transfer rate by using <a href="Double_data_rate" title="Double data rate">double data rate</a> transmission.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup>

</p>

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</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="JTAG" title="JTAG">JTAG</a></div>

<p>Although there are some similarities between SPI and the <a href="JTAG" title="JTAG">JTAG</a> (IEEE 1149.1-2013) protocol, they are not interchangeable. JTAG is specifically intended to provide reliable <a href="Boundary_scan" title="Boundary scan">test access to the I/O pins</a> from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading3"><h3 id="SGPIO">SGPIO</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="SGPIO" title="SGPIO">SGPIO</a></div>

<p><a href="SGPIO" title="SGPIO">SGPIO</a> is essentially another (incompatible) application stack for SPI designed for particular backplane management activities. SGPIO uses 3-bit messages.

</p>

<div class="mw-heading mw-heading3"><h3 id="Intel's_Enhanced_Serial_Peripheral_Interface">Intel's Enhanced Serial Peripheral Interface</h3></div>

<p><a href="Intel" title="Intel">Intel</a> has developed a successor to its <a href="Low_Pin_Count" title="Low Pin Count">Low Pin Count</a> (LPC) bus that it calls the <b>Enhanced Serial Peripheral Interface (eSPI)</b> bus. Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous <a href="Out-of-band_signal" class="mw-redirect" title="Out-of-band signal">out-of-band</a> pins through eSPI, and allow system designers to trade off cost and performance.<sup id="cite_ref-eSPI_37-0" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup>

</p><p>An eSPI bus can either be shared with SPI devices to save pins or be separate from an SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices.<sup id="cite_ref-eSPI_37-1" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>This standard defines an Alert# signal that is used by an eSPI slave to request service from the master. In a performance-oriented design or a design with only one eSPI slave, each eSPI slave will have its Alert# pin connected to an Alert# pin on the eSPI master that is dedicated to each slave, allowing the eSPI master to grant low-latency service, because the eSPI master will know which eSPI slave needs service and will not need to poll all of the slaves to determine which device needs service. In a budget design with more than one eSPI slave, all of the Alert# pins of the slaves are connected to one Alert# pin on the eSPI master in a <a href="Wired-OR" class="mw-redirect" title="Wired-OR">wired-OR</a> connection, which requires the master to poll all the slaves to determine which ones need service when the Alert# signal is pulled low by one or more peripherals that need service. Only after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI slaves needing service and therefore pulling the Alert# signal low.<sup id="cite_ref-eSPI_37-2" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>This standard allows designers to use 1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66 MHz to further allow designers to trade off performance and cost.<sup id="cite_ref-eSPI_37-3" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>Communications that were out-of-band of LPC like <a href="General-purpose_input/output" title="General-purpose input/output">general-purpose input/output</a> (GPIO) and <a href="System_Management_Bus" title="System Management Bus">System Management Bus</a> (SMBus) should be tunneled through eSPI via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.<sup id="cite_ref-eSPI_37-4" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data, short memory cycles with lengths of 1, 2, or 4 bytes that have much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of data which are low overhead as well. This significantly reduces overhead compared to the LPC bus, where all cycles except for the 128-byte firmware hub read cycle spends more than one-half of all of the bus's throughput and time in overhead. The standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction. eSPI slaves are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O cycles, which were introduced by the LPC bus specification, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specification, are not present in eSPI. Therefore, bus master memory cycles are the only allowed DMA in this standard.<sup id="cite_ref-eSPI_37-5" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>eSPI slaves are allowed to use the eSPI master as a proxy to perform flash operations on a standard SPI flash memory slave on behalf of the requesting eSPI slave.<sup id="cite_ref-eSPI_37-6" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.<sup id="cite_ref-eSPI_37-7" class="reference"><a href="#cite_note-eSPI-37"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup>

</p><p>The Intel <a href="Z170" class="mw-redirect" title="Z170">Z170 chipset</a> can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24 MHz instead of the standard 33 MHz.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup>

</p><p>The eSPI bus is also adopted by <a href="AMD_Ryzen" class="mw-redirect" title="AMD Ryzen">AMD Ryzen</a> chipsets.

</p>

<div class="mw-heading mw-heading2"><h2 id="Development_tools">Development tools</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Single-board_computers">Single-board computers</h3></div>

<p><a href="Single-board_computers" class="mw-redirect" title="Single-board computers">Single-board computers</a> may provide <a href="Lead_(electronics)" title="Lead (electronics)">pin</a> access to SPI hardware units. For instance, the <a href="Raspberry_Pi#J8_header_and_general_purpose_input-output_(GPIO)" title="Raspberry Pi">Raspberry Pi's J8 header</a> exposes at least two SPI units that can be used via <a href="Linux" title="Linux">Linux</a> <a href="Device_driver" title="Device driver">drivers</a> or <a href="Python_(programming_language)" title="Python (programming language)">python</a>.

</p>

<div class="mw-heading mw-heading3"><h3 id="USB_to_SPI_adapters">USB to SPI adapters</h3></div>

<p>There are a number of <a href="USB" title="USB">USB</a> adapters that allow a desktop <a href="Personal_computer" title="Personal computer">PC</a> or <a href="Smartphone" title="Smartphone">smartphone</a> with <a href="USB" title="USB">USB</a> to communicate with SPI chips (e.g. CH341A/B<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> based or <a href="FTDI" title="FTDI">FT</a>221xs<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup>). They are used for embedded systems, chips (<a href="FPGA" class="mw-redirect" title="FPGA">FPGA</a>, <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a>, and <a href="System_on_a_chip" title="System on a chip">SoC</a>) and peripheral testing, programming and debugging. Many of them also provide scripting or programming capabilities (e.g. <a href="Visual_Basic" title="Visual Basic">Visual Basic</a>, <a href="C_(programming_language)" title="C (programming language)">C</a>/<a href="C%2B%2B" title="C++">C++</a>, <a href="VHDL" title="VHDL">VHDL</a>) and can be used with open source programs like <a href="Flashrom_(utility)" title="Flashrom (utility)">flashrom</a>, IMSProg, SNANDer or avrdude for <a href="Flash_memory" title="Flash memory">flash</a>, <a href="EEPROM" title="EEPROM">EEPROM</a>, <a href="Bootloader" title="Bootloader">bootloader</a> and <a href="BIOS" title="BIOS">BIOS</a> programming.

</p><p>The key SPI parameters are: the maximum supported frequency for the serial interface, command-to-command latency, and the maximum length for SPI commands. It is possible to find SPI adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length.

</p><p>SPI protocol being a de facto standard, some SPI host adapters also have the ability of supporting other protocols beyond the traditional 4-wire SPI (for example, support of quad-SPI protocol or other custom serial protocol that derive from SPI<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup>).

</p>

<div class="mw-heading mw-heading3"><h3 id="Protocol_analyzers">Protocol analyzers</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Logic_analyzer" title="Logic analyzer">Logic analyzer</a></div>

<p><a href="Logic_analyzers" class="mw-redirect" title="Logic analyzers">Logic analyzers</a> are tools which collect, <a href="Timestamp" title="Timestamp">timestamp</a>, analyze, decode, store, and view the high-speed waveforms, to help <a href="Debugging" title="Debugging">debug</a> and develop. Most logic analyzers have the capability to decode SPI bus signals into high-level protocol data with human-readable labels.

</p>

<div class="mw-heading mw-heading4"><h4 id="Oscilloscopes">Oscilloscopes</h4></div>

<p>SPI <a href="Waveforms" class="mw-redirect" title="Waveforms">waveforms</a> can be seen on <a href="Analog_signal" title="Analog signal">analog</a> channels (and/or via <a href="Digital_signal" title="Digital signal">digital</a> channels in <a href="Oscilloscope#Mixed-signal_oscilloscope" title="Oscilloscope">mixed-signal oscilloscopes</a>).<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> Most <a href="Oscilloscope" title="Oscilloscope">oscilloscope</a> vendors offer optional support for SPI protocol analysis (both 2-, <a class="mw-selflink-fragment" href="#Three-wire">3-</a>, and 4-wire SPI) with triggering.

</p>

<div class="mw-heading mw-heading2"><h2 id="Alternative_terminology">Alternative terminology</h2></div>

<p>Various alternative abbreviations for the four common SPI signals are used. (This section omits overbars indicating active-low.)

</p>

<ul><li>Serial clock

<li>Master Out Slave In (MOSI)

<ul><li>SIMO, MTSR, SPID - correspond to MOSI on both master and slave devices, connects to each other</li>

<li>SDI, DI, DIN, SI, SDA - on slave devices; various abbreviations for <i>serial data in</i>; connects to MOSI on master</li>

<li>SDO, DO, DOUT, SO - on master devices; various abbreviations for <i>serial data out</i>; connects to MOSI on slave</li>

<li>COPI, PICO for <i>peripheral</i> and <i>controller</i>,<sup id="cite_ref-OSHWA_44-0" class="reference"><a href="#cite_note-OSHWA-44"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:5_45-0" class="reference"><a href="#cite_note-:5-45"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> or COTI for <i>controller</i> and <i>target</i><sup id="cite_ref-:1_46-0" class="reference"><a href="#cite_note-:1-46"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup></li></ul></li>

<li>Master In Slave Out (MISO)

<ul><li>SOMI, MRST, SPIQ - correspond to MISO on both master and slave devices, connects to each other</li>

<li>SDO, DO, DOUT, SO - on slave devices; connects to MISO on master</li>

<li>SDI, DI, DIN, SI - on master devices; connects to MISO on slave</li>

<li>Slave Select (SS)

<ul><li>Chip select (CS)</li>

<li>CE (chip enable)</li>

<li>Historical: SSEL, NSS, /SS, SS#</li></ul></li></ul>

<p><a href="Microchip_Technology" title="Microchip Technology">Microchip</a> uses <i>host</i> and <i>client</i> though keeps the abbreviation MOSI and MISO.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup>

</p>

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<ul><li><a href="List_of_network_buses" title="List of network buses">List of network buses</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>

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<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">The earliest definitive mention of a "Serial Peripheral Interface" in bitsavers archives of Motorola manuals is from 1983 (see <a href="#Original_definition">§ Original definition</a>). While some sources on the web allege that Motorola introduced SPI when 68000 was introduced in 1979, however many of those appear to be <a href="Citogenesis" class="mw-redirect" title="Citogenesis">citogenesis</a> or speculation, and Motorola's 1983 68000 manual has no mention of "Serial Peripheral Interface", so the alleged 1979 date does not seem to be reliable information. Please only add a specific design_date if you have a definitive source from Motorola around then.</span>

</li>

<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text">Some slaves require a falling edge of the <span style="text-decoration:overline;">Slave Select</span> signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.</span>

</li>

<li id="cite_note-3wireSDI-9"><span class="mw-cite-backlink">^ <a href="#cite_ref-3wireSDI_9-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-3wireSDI_9-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">Not to be confused with the SDIO (Serial Data I/O) line of the half-duplex implementation of SPI sometimes also called "3-wire" SPI. Here e.g. MOSI (via a resistor) and MISO (no resistor) of a master is connected to the SDIO line of a slave.</span>

</li>

<li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text">Peripherals may allow or require a particular number (or any number) of transfer bytes while selected, as specified in their datasheet.</span>

</li>

<li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text">Left-shifts are used because SPI normally transmits the most-significant bit first. Right-shifts could instead be used to transfer least-significant bit first.</span>

</li>

<li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text">Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips. (<a rel="nofollow" class="external free" href="https://www.ti.com/product/OMAP3530">https://www.ti.com/product/OMAP3530</a>)</span>

</li>

<li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text">Such as the SPI controller on Atmel AT91 chips like the at91sam9G20, which is much simpler than TI's McSPI.</span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<li id="cite_note-:5-45"><span class="mw-cite-backlink">^ <a href="#cite_ref-:5_45-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:5_45-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20220317120519/https://www.ti.com/lit/an/scea091a/scea091a.pdf">"Product Overview - Translate Voltages for SPI"</a> <span class="cs1-format">(PDF)</span>. Archived from <a rel="nofollow" class="external text" href="https://www.ti.com/lit/an/scea091a/scea091a.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2022-03-17.</cite></span>

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<li id="cite_note-:1-46"><span class="mw-cite-backlink">^ <a href="#cite_ref-:1_46-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:1_46-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/www.nxp.com/pages/:SPI">"Serial Peripheral Interface (SPI) Devices"</a>. <i><a href="NXP" class="mw-redirect" title="NXP">NXP</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230601020101/https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/spi-interface-devices:SPI">Archived</a> from the original on 2023-06-01<span class="reference-accessdate">. Retrieved <span class="nowrap">2023-07-22</span></span>.</cite></span>

</li>

<li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><cite id="CITEREFStoicescu" class="citation web cs1">Stoicescu, Alin. <a rel="nofollow" class="external text" href="https://onlinedocs.microchip.com/pr/GUID-EF58F3A9-B49B-4C31-A7EC-B71EBB831870-en-US-5/index.html">"Getting Started with Serial Peripheral Interface (SPI)"</a>. <i><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231221205244/https://onlinedocs.microchip.com/pr/GUID-EF58F3A9-B49B-4C31-A7EC-B71EBB831870-en-US-5/index.html">Archived</a> from the original on 2023-12-21<span class="reference-accessdate">. Retrieved <span class="nowrap">2023-12-21</span></span>.</cite></span>

</li>

</ol></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

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<div class="side-box-text plainlist">Wikimedia Commons has media related to <span style="font-weight: bold; font-style: italic;"><a href="https://commons.wikimedia.org/wiki/Category:Serial_Peripheral_Interface" class="extiw external" title="commons:Category:Serial Peripheral Interface">Serial Peripheral Interface</a></span>.</div></div>

</div>

<ul><li><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/support/software/chipset-software/000020952.html">Intel eSPI (Enhanced Serial Peripheral Interface)</a></li>

<li><a rel="nofollow" class="external text" href="https://www.corelis.com/education/SPI_Tutorial.htm">SPI Tutorial</a></li></ul>

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</style><div id="Technical_and_de_facto_standards_for_wired_computer_buses462" style="font-size:114%;margin:0 4em"><a href="Technical_standard" title="Technical standard">Technical</a> and <a href="De_facto_standard" title="De facto standard"><i>de facto</i> standards</a> for <a href="Wired_communication" title="Wired communication">wired</a> <a href="Bus_(computing)" title="Bus (computing)">computer buses</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_bus" title="System bus">System bus</a></li>

<li><a href="Front-side_bus" title="Front-side bus">Front-side bus</a></li>

<li><a href="Daisy_chain_(electrical_engineering)" title="Daisy chain (electrical engineering)">Daisy chain</a></li>

<li><a href="Control_bus" title="Control bus">Control bus</a></li>

<li><a href="Address_bus" class="mw-redirect" title="Address bus">Address bus</a></li>

<li><a href="Bus_contention" title="Bus contention">Bus contention</a></li>

<li><a href="Bus_mastering" title="Bus mastering">Bus mastering</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a></li>

<li><a href="List_of_interface_bit_rates#Computer_buses" title="List of interface bit rates">List of bus bandwidths</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Standards</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Multibus" title="Multibus">Multibus</a></li>

<li><a href="Unibus" title="Unibus">Unibus</a></li>

<li><a href="VAXBI_bus" class="mw-redirect" title="VAXBI bus">VAXBI</a></li>

<li><a href="System_Management_Bus" title="System Management Bus">SMBus</a></li>

<li><a href="Europe_Card_Bus" title="Europe Card Bus">Europe Card Bus</a></li>

<li><a href="STEbus" title="STEbus">STEbus</a></li>

<li><a href="Zorro_II" title="Zorro II">Zorro II</a></li>

<li><a href="Zorro_III" title="Zorro III">Zorro III</a></li>

<li><a href="Computer_Automated_Measurement_and_Control" title="Computer Automated Measurement and Control">CAMAC</a></li>

<li><a href="FASTBUS" title="FASTBUS">FASTBUS</a></li>

<li><a href="HP_Precision_Bus" title="HP Precision Bus">HP Precision Bus</a></li>

<li><a href="NuBus" title="NuBus">NuBus</a></li>

<li><a href="TURBOchannel" title="TURBOchannel">TURBOchannel</a></li>

<li><a href="InfiniBand" title="InfiniBand">InfiniBand</a></li>

<li><a href="Ethernet" title="Ethernet">Ethernet</a></li>

<li><a href="PCI-X" title="PCI-X">PCI Extended (PCI-X)</a></li>

<li><a href="PCI_Express" title="PCI Express">PCI Express (PCIe)</a></li>

<li><a href="Compute_Express_Link" title="Compute Express Link">Compute Express Link (CXL)</a></li>

<li><a href="Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface (DMI)</a></li>

<li><a href="RapidIO" title="RapidIO">RapidIO</a></li>

<li><a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a></li>

<li><a href="NVLink" title="NVLink">NVLink</a></li>

<li><a href="HyperTransport" title="HyperTransport">HyperTransport</a>

<ul><li><a href="Infinity_Fabric" class="mw-redirect" title="Infinity Fabric">Infinity Fabric</a></li></ul></li>

<li><a href="Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Intel Ultra Path Interconnect</a></li>

<li><a href="Coherent_Accelerator_Processor_Interface" title="Coherent Accelerator Processor Interface">Coherent Accelerator Processor Interface (CAPI)</a></li>

<li><a href="SpaceWire" title="SpaceWire">SpaceWire</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Storage</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Floppy_disk_drive_interface" title="Floppy disk drive interface">Floppy connector</a></li>

<li><a href="Parallel_ATA" title="Parallel ATA">Parallel ATA (PATA)</a></li>

<li><a href="HIPPI" title="HIPPI">HIPPI</a></li>

<li><a href="SATA" title="SATA">Serial ATA (SATA)</a></li>

<ul><li><a href="Parallel_SCSI" title="Parallel SCSI">Parallel</a></li>

<li><a href="ESCON" title="ESCON">ESCON</a></li>

<li><a href="Fibre_Channel" title="Fibre Channel">Fibre Channel</a></li>

<li><a href="SATA_Express" title="SATA Express">SATAe</a></li>

<li>PCI Express (via <a href="Advanced_Host_Controller_Interface" title="Advanced Host Controller Interface">AHCI</a> or <a href="NVM_Express" title="NVM Express">NVMe</a> logical device interface)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Peripheral</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Apple_Desktop_Bus" title="Apple Desktop Bus">Apple Desktop Bus</a></li>

<li><a href="Atari_SIO" title="Atari SIO">Atari SIO</a></li>

<li><a href="Commodore_bus" title="Commodore bus">Commodore bus</a></li>

<li><a href="Lightning_(connector)" title="Lightning (connector)">Lightning</a></li>

<li><a href="IEEE_1284" title="IEEE 1284">IEEE-1284 (parallel port)</a></li>

<li><a href="IEEE_1394" title="IEEE 1394">IEEE-1394 (FireWire)</a></li>

<li><a href="I%C2%B2C" title="I²C">I²C</a> (<a href="ACCESS.bus" title="ACCESS.bus">ACCESS.bus</a>, <a href="Power_Management_Bus" title="Power Management Bus">PMBus</a>, <a href="System_Management_Bus" title="System Management Bus">SMBus</a>)</li>

<li><a href="Parallel_SCSI" title="Parallel SCSI">Parallel SCSI</a></li>

<li><a href="Profibus" title="Profibus">Profibus</a></li>

<li><a href="Camera_Link" title="Camera Link">Camera Link</a></li>

<li><a href="PCI_Express#PCI_Express_External_Cabling" title="PCI Express">External PCIe</a></li>

<li><a href="Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Audio</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="ADAT_Lightpipe" title="ADAT Lightpipe">ADAT Lightpipe</a></li>

<li><a href="Intel_High_Definition_Audio" title="Intel High Definition Audio">Intel HD Audio</a></li>

<li><a href="McASP" title="McASP">McASP</a></li>

<li><a href="TOSLINK" title="TOSLINK">TOSLINK</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Portable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="ExpressCard" title="ExpressCard">ExpressCard</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Embedded</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multidrop_bus" title="Multidrop bus">Multidrop bus</a></li>

<li><a href="CoreConnect" title="CoreConnect">CoreConnect</a></li>

<li><a href="Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a></li>

<li><a href="SLIMbus" title="SLIMbus">SLIMbus</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.<br><span class="noviewer" typeof="mw:File"><span title="Category"></span></span> Category</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-08-04" href="https://en.wikipedia.org/wiki/?title=Serial_Peripheral_Interface&oldid=1304190307">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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